By Rohit Sharma
Three-dimensional (3D) integration of microsystems and subsystems has turn into necessary to the way forward for semiconductor expertise improvement. 3D integration calls for a better figuring out of numerous interconnected structures stacked over one another. whereas this vertical progress profoundly raises the procedure performance, it additionally exponentially raises the layout complexity.
Design of 3D built-in Circuits and platforms tackles all elements of 3D integration, together with 3D circuit and approach layout, new approaches and simulation strategies, substitute verbal exchange schemes for 3D circuits and platforms, program of novel fabrics for 3D structures, and the thermal demanding situations to limit energy dissipation and enhance functionality of 3D platforms. Containing contributions from specialists in in addition to academia, this authoritative text:
- Illustrates assorted 3D integration ways, similar to die-to-die, die-to-wafer, and wafer-to-wafer
- Discusses using interposer expertise and the position of Through-Silicon Vias (TSVs)
- Presents the newest advancements in 3 significant fields of thermal administration for multiprocessor systems-on-chip (MPSoCs)
- Explores ThruChip Interface (TCI), NAND flash reminiscence stacking, and rising applications
- Describes large-scale integration trying out and cutting-edge low-power checking out solutions
Complete with experimental result of chip-level 3D integration schemes demonstrated at IBM and case reports on complicated complementary metal–oxide–semiconductor (CMOS) integration for 3D built-in circuits (ICs), layout of 3D built-in Circuits and structures is a pragmatic reference that not basically covers a wealth of layout concerns encountered in 3D integration but in addition demonstrates their effect at the potency of 3D systems.
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Additional info for Design of 3D Integrated Circuits and Systems
Evaporated 3 μm/3 μm thick Cu/Sn and immersion Au plating over electroless Ni plating were used for the bonding microbumps and bonding pads. X-ray photoelectron spectroscopy (XPS) was used to study the surface elemental composition of the micro-bumps and pad surfaces before and after the cleaning processes. 13(a)). 13(b). After the surface treatments, the upper and lower silicon pieces were bonded at 260°C without flux by using a bonding tool. 13(c). Hydrogen radical treatments with higher temperatures gave higher average shear strength.
Therefore, the interconnections and layering processes are performed sequentially. Different processing solutions such as beam recrystallization, selective epitaxial growth (SEG) [25–27], and solid phase crystallization [28–31] have been used in bottom-up approaches to 3D integration. 3(c–d) shows schematics of multiple silicon layers using silicon epitaxial growth. The major problem is the high processing temperature (~1,000°C) for silicon epitaxial growth, and this significantly affects the lower layers of the devices, especially the layers with m etallization.
Annealing could reduce the Cu extrusion, but induce several issues such as Cu voids formation and diffusion of Cu atoms. Because there is a significant mismatch in the CTE between Cu and bulk silicon, Cu TSV induces stress on its surroundings. In this case, a device prohibition area called keep-out zone (KOZ) is used, and must be included in the circuit layouts . 7 The impact of TSV and thin silicon substrate. (From Sakuma, J. Inst. Electrical Eng. , 131(1), 19–25 (2011) (in Japanese). 7) .